The present invention relates generally to three dimensional integrated circuits. More particularly, the present invention relates to a specific configuration for three dimensional integrated circuits and a method of fabricating the same.
In order to increase circuit density, semiconductor manufacturers have continued to reduce the size of various integrated circuit elements and interconnections to the point where the limits of current technology are being reached. It would, therefore be desirable to provide a multi-level integrated chip of very small dimensions with large amounts of electronic devices than are currently feasible.
Accordingly, it is an object of the present invention to provide a multi-level chip whose individual layers may be fabricated independently of one another and bonded together after all incompatible processing steps have been performed.